1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. In particular, the invention relates to a method for manufacturing a bottom gate thin film transistor that includes a channel forming region having a thickness smaller than that of a source region and a drain region.
2. Description of the Related Art
It is known that in a thin film transistor (hereinafter referred to as a TFT), the S value that indicates the switching characteristics (subthreshold characteristics) of a transistor can be improved (i.e., reduced) by reducing the thickness of a channel forming region. The S value here is a gate voltage (potential difference between a source region and a gate electrode based on the potential of the source region) that is required to increase a current between the source region and a drain region (subthreshold current) by one digit. When the S value decreases, the slope of the subthreshold current to the gate voltage increases and excellent switching characteristics are obtained. A TFT with a smaller S value is advantageous in that power consumption is suppressed by reducing the operating voltage and the off leak current is reduced. However, when the whole semiconductor film is reduced in thickness in order to reduce the thickness of the channel forming region, the thickness of the source region and the drain region is also reduced, the sheet resistance between the source region and the drain region increases, and the contact resistance between the source region and the drain region and between the source electrode and the drain electrode increases. Therefore, it is preferable to reduce the thickness of the channel forming region while maintaining an adequate thickness of the source region and the drain region.
Patent Document 1 discloses an example of such a method as to reduce the thickness of only a channel forming region. According to the method disclosed in Patent Document 1, the thickness of a channel forming region is reduced by the following steps. First, a projection is formed over an insulating substrate at a position corresponding to a channel forming region formed later. Such a projection can be formed by removing part of the surface of the insulating substrate by etching. Then, a semiconductor layer made of silicon or the like is deposited over the insulating substrate including the projection so as to have a predetermined thickness and have a protruding portion at a position corresponding to the projection. Then, an insulating film with a flat surface is formed over the semiconductor layer. A photoresist film is formed over the insulating film at a position corresponding to the projection and ions are implanted into the semiconductor layer using the photoresist film as a mask, thereby forming a source region and a drain region in the semiconductor layer on both sides of the projection. After that, the photoresist film is removed. Then, the insulating film as well as the upper part of the protruding portion (i.e., channel forming region) of the semiconductor layer is removed by etching to flatten the surface of the semiconductor layer, thereby reducing the thickness of the channel forming region. The insulating film and the semiconductor layer are removed by plasma etching in an atmosphere containing a mixed gas of SF6 and CHF3. In the method as disclosed in Patent Document 1, in order to reduce the thickness of the protruding portion of the semiconductor layer corresponding to the projection over the upper surface of the insulating substrate, etching is performed until the whole surface of the semiconductor layer is exposed and flattened. Accordingly, the source region and the drain region as well as the protruding portion (channel forming region) are in danger of being etched. In addition, plasma etching may cause characteristic deterioration such as damage to the upper part of the semiconductor layer, transformation into an amorphous state, and increase in resistance due to these damages.
Patent Document 2 discloses another method for reducing the thickness of a channel forming region. According to Patent Document 2, a photosensitive resist provided over a semiconductor layer (operation layer) is exposed to light using a halftone mask so that the thickness of the photosensitive resist over a channel forming region of a TFT forming region is smaller than that of the photosensitive resist in a region outside the channel forming region. Then, the photosensitive resist is further processed to remove the photosensitive resist on the channel forming region, and wet etching or dry etching is applied using the remaining part of the photosensitive resist as a mask, thereby reducing the thickness of the channel forming region. However, such a selective exposure of a photosensitive resist using a halftone mask requires a complicated process, which may increase the production cost.
It is also known that in manufacturing of a thin film transistor, an amorphous silicon film is formed and then irradiated with laser light to be melted and crystallized, thereby forming a polycrystalline silicon film that serves as an active region (Patent Document 3).    [Patent Document 1] Japanese Published Patent Application No. H5-110099    [Patent Document 2] Japanese Published Patent Application No. 2004-281687    [Patent Document 3] Japanese Published Patent Application No. H11-111998